1. Field of the Invention
The present invention generally relates to a memory system that utilizes a buffering structure to isolate a memory controller from memory devices, and in particular, to a system and method for providing reliable transmission of informationxe2x80x94such as data, status, command, and addressxe2x80x94in a buffered memory system. The memory devices may, for example, be dynamic random access memory (DRAM) devices.
2. Related Art
A typical memory system includes a memory controller and memory devices, such as DRAMs, coupled thereto. In some systems, a processor performs memory controller functions. As used herein, the term memory controller includes such a processor. The memory controller and memory devices are coupled together using a memory interface. The memory interface provides communication between the memory controller and the memory devices. The memory interface may contain address bus lines, command signal lines, and data bus lines. Increasing demand for higher computer performance and capacity has resulted in a demand for a larger and faster memory. However, as operating speed and the number of memory modules connected to the chipset increase, the resultant increased capacitive loading may place substantial limits on the size and speed of the memory.
A drawback to memory devices directly connected to a memory bus is that there is no voltage level isolation between the memory devices and the memory controller and no capacitive load isolation between the memory bus and the memory devices. As such, it is required that each component operates with the same interface voltage and frequency. Therefore, the memory controller is manufactured to operate with specific memory devices meeting these parameters. Conversely, the memory devices are also utilized only with a memory controller having the same interface voltage and operating frequency. Therefore, the memory devices utilized with memory controllers are limited to only those having the same interface voltage and operating frequency as that of the memory controller.
Moreover, as the frequency of signals travelling through the memory increases, inherent delays between an external, system or reference clock and the time data is valid for either the memory controller or the memory devices becomes a crucial constraint. The time data is valid for the memory controller is important when the memory controller is expecting data from the memory device, such is in a read operation. The time data is valid for the memory devices is important when the memory devices are expecting data from the memory controller, such as in a write operation. The delay can be large enough to make a following clock cycle overlap the data. That is, the delay becomes large enough for data not to be ready for the memory controller or the memory device during one cycle, and it essentially becomes xe2x80x9coff-syncxe2x80x9d.
In other memory system, solutions have evolved to solve the xe2x80x9coff-syncxe2x80x9d difficulties. Prior art designs, such as a registered dual in line memory module (xe2x80x9cregistered DIMMxe2x80x9d) system, have addressed the difficulties by utilizing a discrete phase lock loop chip. The input clock to the registered DIMM module enters the discrete chip, the output of which is used to drive registers in the registered DIMM system. However, memory controller and memory devices within a registered DIMM system are constrainted to have the same interface voltage and operating frequency. The cost requiring specifically designed memory devices to match the memory controller in a registered DIMM system, and vice versa, creates high development expenses, as well as limiting the interchangeability of various existing memory components. Therefore, there is a need for a system and method to provide a memory system that would not only provide reliable transmission and reduce clock-insertion and propagation delay, but also would not require each component to operate with the same interface voltage and frequency.